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philips semiconductors PCA9504A glue chip 4 product data supersedes data of 2003 nov 10 2004 may 11 integrated circuits
philips semiconductors product data PCA9504A glue chip 4 2 2004 may 11 features ? dual, strapping, selectable feature sets ? audio-disable circuit ? mute audio circuit ? 5 v reference generation ? 5 v standby reference generation ? hd single color led driver ? ide reset signal generation/pcirst# buffers ? pwrok (pwrgd_3v) signal generation ? power sequencing / backfeed_cut ? power supply turn on circuitry ? rmsrst# generation ? voltage translation for ddc to vga monitor ? hsynch / vsynch voltage translation to vga monitor ? 3-state buffers for test ? extra gp logic gates ? power led drivers ? flash flush# / init# circuit ? 5 v i 2 c to 3.3 v smbus conversion to 400 khz ? requires both 3.3 v and 5.0 v operating voltages ? 0 to +70 c operating temperature range ? esd protection exceeds 1000 v hbm per jesd22-a114 and 750 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offered: tssop56 description the PCA9504A glue chip 4 is a highly integrated and cost-efficient custom asic that reduces logic part count, overall component cost, and board space requirements for pc designers and manufacturers. the glue chip 4 supports the latest generation of high-volume platforms based on intel ? processors and chipsets that require additional external circuitry in order to function properly. it is used on entry servers/workstations (840 and 860 chipsets), high-end desktops (820 and 850 chipsets), as well as mid range (815, 830 and 845 chipsets) and low-end (810 chipset) motherboards. some of these functionalities include meeting timing specifications, buffering signals, and switching between power wells. the PCA9504A glue chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin tssop device. the glue chip 4 typically resides on the motherboard close to the i/o controller hub (ich) and is optimized for the intel 82801ba i/o controller hub (ich2). pin configuration sw00578 1 2 3 4 5 6 7 8 9 10 11 12 45 46 47 48 49 50 51 52 53 54 55 56 vref3in v_3p3_stby gpo_flush_cache/gp1_in a20m/gp1_inb init/gp1_ina flush_out_cpu/gp1_out init_out/gp2_out clk_in sel_33_66 gnd gp3_out gp3_in strap vccp_vref vsync_5v hsync_5v vsync_3v ref5v_stby hsync_3v aud_shdn mute_aud vref5in pcirst 13 14 15 16 17 18 39 40 41 42 43 44 pcrist_out aud_en aud_rst ide_rstdrv 3v_ddcscl ref5v rsmrst gnd test_en grn_led 5v_ddcscl 19 38 ylw_led 3v_ddcsda 20 21 22 23 24 25 32 33 34 35 36 37 5v_ddcsda cpu_present slp_s3 ps_on hd_led ylw_blnk sck_bjt_gate grn_blnk pwrgd_3v fprst pwrgd_ps primary_hd 26 31 flush_out_fwh scsi 27 30 latched_backfed_cut secondary_hd 28 29 backfeed_cut gnd v_5p0_stby slp_s5 ordering information package temperature range order code topside mark drawing number 56-pin plastic tssop 0 c to +70 c PCA9504Adgg PCA9504Adgg sot364-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 3 pin description pin(s) symbol function 1 3i vref3in 3.3 v input 2 p v_5p0_stby 5 v system standby power supply 3 p v_3p3_stby 3 v system standby power supply 4 3iu gpo_flush_cache / gp2_in gpo from sio / ich2 / buffer 2 input 5 ref a20m / gp1_inb a20m signal from ich2 / nand 1 input b 6 ref init / gp1_ina init signal from the ich2 / buffer 1 input a 7 5v od flush_out_cpu / gp1_out open drain signal, goes to the cpu / nand 1 output 8 5v od init_out / gp2_out delayed init signal into the cpu / buffer 2 output 9 3i clk_in either 33mhz or 66mhz clock, based on sel_33_66 pin 10 3iu sel_33_66 strapping option for 33mhz or 66mhz clk_in 11, 29, 43 g gnd ground 12 3i pcrist pci reset signal 13 3o pcrist_out copy of pcrist, increased drive-strength 14 3iu aud_en audio enable input (gpo from ich2 / sio) 15 3o aud_rst audio reset output 16 5o ide_rstdrv ide reset output, 5 v push/pull 17 3iod 3v_ddcscl ddcscl input/output 3.3 v side 18 5iod 5v_ddcscl ddcscl input/output 5 v side 19 3iod 3v_ddcsda ddcsda input/output 3.3 v side 20 5iod 5v_ddcsda ddcsda input/output 5 v side 21 3iu cpu_present cpu present signal from the processor 22 3i slp_s3 signal from ich2 for transitioning to the s3 power state 23 5v od ps_on power supply turn-on signal 24 5v od hd_led hard drive front panel led output 25 5iu primary_hd ide primary drive active input 26 5iu scsi scsi drive active input 27 5iu secondary_hd ide secondary drive active input 28 5v od backfeed_cut signal used for str circuitry 30 5o latched_backfeed_cut signal used for str circuitry 31 5v od flush_out_fwh open drain signal, goes to the fwh 32 5iu pwrgd_ps power good signal from power supply 33 5iu fprst reset signal from the front panel 34 3o pwrgd_3v 3.3 v power good output 35 5v od sck_bjt_gate gate signal from the sck bjt in suspend to ram 36 3i slp_s5 signal from the ich2 for transitioning to the s5 power state 37 3iu grn_blnk power led input, from sio gpio 38 3iu ylw_blnk power led input, from sio gpio 39 5v od ylw_led power led output 40 5v od grn_led power led output 41 5id test_en test enable, 100k internal pull-down to gnd 42 3o rsmrst reset for the ich2 resume well 44 ao ref5v highest system supply reference voltage 45 5i vref5in 5v system primary supply input 46 3iu mute_aud signal from sio to mute audio on power up/down 47 5o aud_shdn signal to audio amp to signal shutdown 48 ao ref5v_stby highest system standby voltage 49 3i hsync_3v hsynch input from chipset video
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 4 pin description continued pin(s) symbol function 50 3i vsync_3v vsynch input from chipset video 51 5o hsync_5v hsynch output to monitor 52 5o vsync_5v vsynch output to monitor 53 ai v ccp _vref analog voltage reference for determining init/a20m input thresh- olds 54 3iv/3o strap strapping option for gp or flush mode (internal pull-up resistor) note 1 55 5i gp3_in generic logic gate 3 input 56 5v od gp3_out generic logic gate 3 output note: 1. the pin is internally pulled up to default to flush mode. type description 3i 3.3 v input signal 3iu 3.3 v input signal with internal pull-up 5i 5 v input signal 5iu 5 v input signal with internal pull-up 5id 5 v input signal with internal pull-down p power (input) g ground (input) 3o 3.3 v output signal 5o 5 v output signal 3v od 3.3 v open-drain output signal 5v od 5 v open-drain output signal ao analog output ai analog input 3iod 3.3 v input/output open-drain 5iod 5 v input/output open-drain refl input voltage levels referenced to v ccp _vref function tables strapping selection pin strap (pin 54) 1 mode 1 pin name & (pin number) 1 no connect flush gpo_flush_cache (4) 1 no connect flush a20m (5) 1 no connect flush init (6) 1 no connect flush flush_out_cpu (7) 1 no connect flush init_out (8) 0 gnd gp gp2_in (4) 0 gnd gp gp1_inb (5) 0 gnd gp gp1_ina (6) 0 gnd gp gp1_out (7) 0 gnd gp gp2_out (8) note: 1. the pin is internally pulled up to default to flush mode.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 5 typical application gpo_flush_cache_pu* 4 h_init_pu* 6 p_pcirst* 12 tp_glue4_ddcsol_3v 17 ck_66m_glue 8 cpu_present* 21 ide_pri_act* 25 nc 26 ide_sec_act* 27 gpio_a ud_en 14 nc 47 tp_glue4_testen_41 41 glue4_sel_33_66_r 10 tp_glue4_ddcsd a_5v 20 pwrgd_ps 32 tp_glue4_ddcsd a_3v 19 glue_fp_rst_r* 33 tp_glue4_ddcscl_5v 18 slp_s5* 36 slp_s3* 22 gpio_grn_blnk 37 gpio_yl w_blnk 38 tp_glue4_hsync3v 49 tp_glue4_vsync3v 50 aud_midi_out_b_pu 5 v5ref_sus 48 vccp_vref 53 55 gpo_flush_cache/gp2in init/gp1_ina pcirst 3v_ddc5cl clk_in cpu_present primar y_hd scsi second ar y_hd aud_en aud_shdn test_en sel_3366 5v_ddcsd a pwrgd_ps 3v_ddc5d a fprst 5v_ddcscl slp_55 slp_s3 grn_blnk ylw_blnk hsync_3v vsync_3v a20m/gp1_inb ref5v_stby vccp_vref gp3_in in in in in in in in in in in in in in in in in in out in in in vref5in vref3in v_5p0_stby v_3p3_stby ref5v hd_led pcirst_out aud_rst mute_a ud sck_bjt_ga te flush_out_fwh flush_out_cpu/gp1_out init_out/gp2_out ide_rstdr v backfeed_out latched_backfeed_out pwrgd3v ps_on rsmrst yl w_led grn_led hsync_5v vsync_5v strap gp3_out gnd gnd gnd 45 glue4_vref5in_r 1 glue4_vref5in_r 2 v_5p0_stby 3 v_3p3_stby 44 v_ref5v 24 hd_led* 13 p_rst_slo ts_r* 15 tp_a ud_rst* 46 mute_a ud_pni* 35 tpsckbjt_ga te_enable 31 tp_glue4_flush_out_fwh 7 tp_glue4_gp1_out 8 tp_glue4_8 16 ide_rst* 28 backfeed_cut 30 vreg_backfeed_u4 34 pwrgd_3v 23 ps_on* 42 rsmrst* 39 gpio_yl w_blnk_hdr 40 gpio_grn_blnk_hdr 51 tp_glue4_hsync5v 52 tp_glue4_vsync5v 54 glue4_strap 56 pwrgd_ps_buff 11 29 43 v_383_stby pwrgd_ps has weak internal pullup ic out out out out out out out out out out out out v_3p3_stby v cc 3 v cc v_3p3_stby pin function 1 vref3in 2 5vsb 3 3vsb 4 gp2_in 5 gp1_inb 6 gp1_ina 9 clk_in 10 sel_33_66 12 pcirst* 14 aud_en 17 3v_ddcscl 18 5v_ddcscl 19 3v_ddcsd a 20 5v_ddcsd a 21 cpu_present* 22 slp_s3* 25 primar y_hd* 26 sc5i* 27 second ar y_hd* 32 pwrgd_ps 33 fprst* 36 slp_s5* 37 grn_blnk 38 yl w_blnk 41 test_en 45 vref5in 46 mute_a ud* 49 hsynch_3v 50 vsynch_3v 53 vccp_vref 54 strap 55 gp3_in glue 4 inputs glue chip 4 49.9 k w 1 k w sw01083 100 w 1 k w 10 k w 10 k w 10 k w figure 1. typical application
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 6 absolute maximum ratings 1 symbol parameter condition limits unit symbol parameter condition min max unit v_5p0_stby dc 5.0v supply 0.5 +6.0 v v_3p3_stby dc 3.3v supply 0.5 +6.0 v v i (5v) dc input voltage (5 v pins) note 2 0.5 v_5p0_stby+0.5 v v o (5v) output voltage range (5 v pins) note 2 0.5 v_5p0_stby+0.5 v v i (3.3v) dc input voltage (3.3 v pins) note 2 0.5 v_3p3_stby+0.5 v v o (3.3v) output voltage range (3.3 v pins) note 2 0.5 v_3p3_stby+0.5 v spd supply power dissipation 100 mw esd static discharge voltage 2000 v t stg storage temperature range 55 +150 c t otr operating temperature range 0 70 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operatio n of the device at these or any other condition beyond those indicated under arecommended operating conditiono is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage rating may be exceeded if the input and output current ratings are observed. recommended operating conditions symbol parameter conditions limits unit symbol parameter conditions min max unit v dd3 dc 3.3 v supply voltage 3.0 3.6 v v ddl dc 2.5 v supply voltage 4.75 5.25 v v i dc input voltage 0 v dd3 v v o dc output voltage 0 v ddl v dd3 v t a operating ambient temperature range in free air 0 +70 c
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 7 dc characteristics v_5p0_stby = 5 v 5%; v_3p3_stby = 3.3 v 10% limits symbol parameter test condition t amb = 0 c to +70 c unit min typ max strap v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ih input leakage high 1 1 m a v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 3 ma 2.4 v i il input leakage low 88 26 m a aud_en v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i il input leakage low v il = 0 v 88 26 m a i ih input leakage high 1 1 m a pcirst v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage 1 1 m a hys input hysteresis 400 mv mute_aud v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i ih input leakage high 1 1 m a i il input leakage low v il = 0 v 88 26 m a vref5in v ih high-level input voltage 0.85*v5p 0_stby v v il low-level input voltage 0.2*v5p 0_stby v i l input leakage 1 1 m a vref3in v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage 1 1 m a primary_hd v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i il input leakage low v il = 0 v 88 26 m a i ih input leakage high v ih = 5vsb 1 1 m a secondary_hd v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i il input leakage low v il = 0 v 88 26 m a
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 8 symbol unit limits test condition parameter symbol unit t amb = 0 c to +70 c test condition parameter symbol unit max typ min test condition parameter i ih input leakage high v ih = 5vsb 1 1 m a scsi v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i il input leakage low v il = 0 v 88 26 m a i ih input leakage high v ih = 5vsb 1 1 m a fprst v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i il input leakage low v il = 0 v 88 26 m a i ih input leakage high v ih = 5vsb 1 1 m a pwrgd_ps v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i il input leakage low v il = 0 v 88 26 m a i ih input leakage high v ih = 5vsb 1 1 m a gpo_flush_cache/gp2_in v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage v il = 0 v 88 26 m a i ih input leakage v ih = 5 v 1 1 m a init / gp1_ina (gp mode) v ih high-level input voltage part is strapped for gp mode 2.4 v v il low-level input voltage part is strapped for gp mode 0.8 v i l input leakage part is strapped for gp mode 1 1 m a vccp_v ref bias voltage gp mode 1.95 2.1 v init / gp1_ina (flush mode) v ih high-level input voltage flush mode 1.5 v v il low-level input voltage flush mode 0.4 v i il input leakage flush mode 1 1 m a vccp_v ref bias voltage flush mode 0.95 1.1 v
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 9 symbol unit limits test condition parameter symbol unit t amb = 0 c to +70 c test condition parameter symbol unit max typ min test condition parameter a20m / gp1_inb v ih high-level input voltage flush mode 1.5 v v il low-level input voltage flush mode 0.4 v i il input leakage flush mode 1 1 m a vccp_v ref bias voltage flush mode 0.95 1.1 v v ih high-level input voltage gp mode 2.4 v v il low-level input voltage gp mode 0.8 v i l input leakage gp mode 1 1 m a vccp_v ref bias voltage gp mode 1.95 2.1 v clk_in v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v hys input hysteresis 250 mv i l input leakage 1 1 m a sel_33_66 v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v hys input hysteresis 400 mv i ih input leakage 1 1 m a i il input leakage v il = 0 v 88 26 m a slp_s3 v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v hys input hysteresis 400 mv i l input leakage 1 1 m a slp_s5 v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v hys input hysteresis 400 mv i l input leakage 1 1 m a cpu_present v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v hys input hysteresis 400 mv i ih input leakage v ih = 3vsb 1 1 m a i il input leakage v il = 0 v 88 26 m a test_en v ih high-level input voltage 0.7*5vsb v v il low-level input voltage 0.2*5vsb v hys input hysteresis 400 mv i ih input leakage v il = 0 v 1 1 m a i il input leakage v ih = 5vsb 20 88 m a
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 10 symbol unit limits test condition parameter symbol unit t amb = 0 c to +70 c test condition parameter symbol unit max typ min test condition parameter hsync_3v v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage 1 1 m a vsync_3v v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage 1 1 m a grn_blnk v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i ih input leakage 1 1 m a i il input leakage v il = 0 v 88 26 m a ylw_blnk v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i ih input leakage 1 1 m a i il input leakage v il = 0 v 88 26 m a gp3_in v ih high-level input voltage 2.2 v v il low-level input voltage 0.8 v i l input leakage 1 1 m a aud_rst v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 3 ma 2.4 v i oz off state output current 1 1 m a aud_shdn v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 6 ma 2.4 v i oz off state output current 1 1 m a ref5v v out5 low-level output voltage v ref5in > 1.5 v v ref5in 0.05 v ref5in + 0.05 v v out3 high-level output voltage v ref3in > 1.5 v v ref3in 0.05 v ref3in + 0.05 v i outl off state output current 20 20 m a ref5v_stby v out5 low-level output voltage v_5p0_stby > 1.5 v v_5p0_stby 0.05 v_5p0_stby + 0.05 v v out3 high-level output voltage v_5p0_stby > 1.5 v v_5p0_stby 0.05 v_5p0_stby + 0.05 v i outl off state output current 20 20 m a hd_led v ol low-level output voltage i ol = 12 ma 0.4 v i oz off state output current 1 1 m a
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 11 symbol unit limits test condition parameter symbol unit t amb = 0 c to +70 c test condition parameter symbol unit max typ min test condition parameter ide_rstdrv v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 6 ma 2.4 v i oz off state output current 1 1 m a pcirst_out v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 3 ma 2.4 v i oz off state output current 1 1 m a prwgd_3v v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 3 ma 2.4 v i oz off state output current 1 1 m a init_out / gp2_out v ol low-level output voltage i ol = 12 ma 0.4 v i oz off state output current 1 1 m a flush_out_cpu / gp1_out v ol low-level output voltage i ol = 12 ma 0.4 v i oz off state output current 1 1 m a backfeed_cut v ol low-level output voltage i ol = 6 ma 0.4 v i oz off state output current 1 1 m a flush_out_fwh v ol low-level output voltage i ol = 6 ma 0.4 v i oz off state output current 1 1 m a latched_backfeed_cut v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 6 ma 2.4 v i oz off state output current 1 1 m a ps_on v ol low-level output voltage i ol = 6 ma 0.4 v i oz off state output current 1 1 m a rsmrst v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 3 ma 2.4 v i oz off state output current 1 1 m a vtrip 5vsb low trip voltage 1.8 3.5 v sck_bjt_gate v ol low-level output voltage i ol = 6 ma 0.4 v i oz off state output current 1 1 m a
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 12 symbol unit limits test condition parameter symbol unit t amb = 0 c to +70 c test condition parameter symbol unit max typ min test condition parameter 3v_ddcsda v ol low-level output voltage i ol = 6 ma 0.4 v i h input leakage 5v_ddcsda = v dd 1 2.5 m a i oz off state output current 1 1 m a 5v_ddcsda v ol low-level output voltage i ol = 6 ma 0.4 v i h input leakage 3v_ddcsda = v dd 1 2.5 m a i oz off state output current 1 1 m a 3v_ddcscl v ol low-level output voltage i ol = 6 ma 0.4 v i h input leakage 5v_ddcscl = v dd 1 2.5 m a i oz off state output current 1 1 m a 5v_ddcscl v ol low-level output voltage i ol = 6 ma 0.4 v i h input leakage 3v_ddcscl = v dd 1 2.5 m a i oz off state output current 1 1 m a hsync_5v v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 6 ma 3.8 v i oz off state output current 1 1 m a vsync_5v v ol low-level output voltage i ol = 6 ma 0.4 v v oh high-level output voltage i oh = 6 ma 3.8 v i oz off state output current 1 1 m a grn_led / ylw_led v ol low-level output voltage i ol = 24 ma 0.4 v i oz off state output current 1 1 m a gp3_out v ol low-level output voltage i ol = 6 ma i oz off state output current 1 1 m a
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 13 ac characteristics v cc1 = 3.3 v; v cc = 5.0 v limits symbol parameter t amb = 0 c to +70 c units notes min typ max t reset rsmrst 4.0 100 ms t reset_fall rsmrst 100 ns t phl /t plh propagation delay aud_en to aud_rst pcirst to aud_rst pcirst to ide_rstdrv pcirst to pcirst_out 1.0 11.0 ns t plh /t phl propagation delay mute_aud to mute_shdn 2.5 6.0 ns t plh /t phl propagation delay pwrgd_ps to pwrgd_3v fprst to pwrgd_3v 4.5 11.0 ns t plh /t phl propagation delay hsync_3v to hsync_5v vsync_3v to vsync_5v 2.0 5.0 ns t plh /t phl propagation delay pwrgd_ps to sck_bjt_gate fprst to sck_bjt_gate 1.0 6.0 ns t plz /t pzl open drain prop delay primary_hd to hd_led primary_hd to hd_led primary_hd to hd_led 1.0 5.0 ns t plz /t pzl open drain prop delay gp1_ina to gp1_out gp2_ina to gp1_out 3.0 25.0 ns t plz /t pzl open drain prop delay gp2_in to gp2_out 3.0 7.0 ns t plz /t pzl open drain prop delay gp3_in to gp3_out 1.0 4.0 ns t plz /t pzl open drain prop delay slp_s3 to backfeed_out prwgd_ps to backfeed_out 1.0 6.0 ns t plz /t pzl open drain prop delay cpu_present to ps_on 2.0 10.0 ns t plz /t pzl open drain prop delay slp_s3 to ps_on 2.0 10.0 ns t plz /t pzl open drain prop delay backfeed_out to latched_backfeed_out 2.0 11.0 ns t plz /t pzl open drain prop delay slp_s5 to ylw_led slp_s5 to grn_led ylw_blnk to ylw_led grn_blnk to grn_led 1.0 5.0 ns t plz /t pzl open drain prop delay 3v_ddosda to 5v_ddosda 3v_ddosda to 5v_ddosda 1.0 5.0 ns t r , t f rise and fall times hsync_5v vsync_5v 3.5 ns t r , t f rise and fall times latched_backfeed_out 1.0 m s
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 14 waveforms v ol t plh t phl output v m v m v m v ih v il input v oh v m sw00720 waveform 1. t plz t pzl v i input gnd v dd output low-to-off off-to-low v ol v m v m t pzh v x sw00722 t phz waveform 2. v m v m v m v m input t phl t plh sf01443 output waveform 3. t plz t pzl v i input gnd v dd output low-to-off off-to-low v ol v m v m t pzh v x sw00721 t phz v dd waveform 4.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 15 5v reference generation supply ref5v vref5in < vref3in vref3in vref5in > vref3in vref5in sw00580 3.3 v vref3in 5 v vref5in 5 v 3.3 v ref5v figure 1. ref5v when vref3in ramps before vref5in sw00581 3.3 v vref3in 5 v vref5in 5 v ref5v figure 2. ref5v when vref5in ramps before vref3in
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 16 5v standby reference generation standby supply ref5v_stby v_5po_stby v_3p3_stby v_3p3_stby v_5po_stby v_3p3_stby v_5po_stby sw00582 3.3 v v_3p3_stby 5 v v_5p0_stby 5 v 3.3 v ref5v_stby figure 3. ref5v_stby when v_3p3_stby ramps before v_5po_stby sw00583 v_3p3_stby v_5p0_stby ref5v_stby figure 4. ref5v_stby when v_5po_stby ramps before v_3p3_stby
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 17 flush out* / init out* circuit sw00584 ich_a20m* ich_init* gpo_flush_cache* vccp_vref vccp 100 w 1 m f glue chip v_vccp vcc3 cpu fwh h_flush_out_cpu* h_flush_out_fwh* h_init_out* 50 w 1 k w 1 k w 1 k w figure 5. block diagram for flush_out*/init_out* circuit case a20m* gpo flush cache* init* flush out cpu* flush out fwh* init out* 1 1 falling edge 0 0 (for t1) 0 (for t1) 0, hi-z, then 0 (delayed by t1-t, then active for 2*t) 2 1 falling edge 1 0 (for t1) 0 (for t1) hi-z, 0 (delayed by t1-t, then active for 2*t) 3 x 1 0 hi-z hi-z 0 4 x 1 1 hi-z hi-z hi-z 5 0 falling edge 1 hi-z hi-z hi-z 6 0 falling edge 0 hi-z hi-z 0 note: 1. nominal value timings with tolerances are listed in the dc characteristics table for t and t1. all hi-z outputs are shown as 1's or high in the following diagrams.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 18 sw00585 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* tt t1 t1 figure 6. waveforms for case 1 sw00586 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* tt t1 t1 figure 7. waveforms for case 2
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 19 sw00587 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* figure 8. waveforms for case 3 sw00588 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* figure 9. waveforms for case 4
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 20 sw00589 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* figure 10. waveforms for case 5 sw00590 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* figure 11. waveforms for case 6
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 21 sw00591 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* tt t1 t t1 t1 figure 12. waveforms for case 7 sw00592 a20m* gpo_flush_cache* init* flush_out_cpu* flush_out_fwh* init_out* tt t1 t1 figure 13. waveforms for boundary gpo_flush_cache* case ? timings should remain the same for both a 66 mhz or 33 mhz clk_in input. ? the boundary condition for init listed above, is a special case where immediately following the flush_out*, init_out* cycle, the ich2 asserts init* into the glue chip. ? the boundary condition for gpo_flush_cache* listed above, is a special case where immediately following the first assertion of gpo_flush_cache*, the gpo is de-asserted, then re-asserted again before the timings have had a chance to complete. note: 1. nominal timing values with tolerances are listed in the dc characteristics table. gpo_flush_cache* input to logic, gpo from the ich2, programmed active low. init* input to logic, init* signal from the ich2. a20m* input to logic, a20m* signal from the ich2. flush_out_cpu* output of logic, route to cpu flush* pin. flush_out_cpu* output of logic, routed to fwh init* pin. init_out* output of logic, routed to cpu init* pin.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 22 sw00593 latched_backfeed_cut backfeed_cut* slp_s5* t1 t2 figure 14. power up signal sequencing power up signal sequencing is shown in figure 14. backfeed_cut* is following the power rail up to its final value. latched_backfeed_cut should stay low, never turning on. slp_s5* goes to its high value when the power rails have stabilized, 25 msec after power on. backfeed_cut* is pulled low a period t1 after slp_s5* goes high. t1 can be as short as 1msec. typical measured values are 200 msec. t1 and t2 are guaranteed by the inherent design of the system and are not controlled by glue chip. sw00594 latched_backfeed_cut backfeed_cut* tpropr tr tpropf tf slp_s5* figure 15. 1st sequence timing the first possible sequence is with slp_s5*staying high and backfeed_cut* transitioning from low to high, remaining high for an undetermined period and then going back to low and the system is back at the end of the power-up sequence. the power-up sequenc e is shown in figure 15. during these backfeed_cut* transitions, the propagation delays, rise and fall times, and going into regulat ion times latched_backfeed_cut are as described in figure 16. the first s equence starts can start at the end of the power-up sequence at any time. sw00595 latched_backfeed_cut backfeed_cut* t3 tpropf slp_s5* tpropr tr tf t4 figure 16. 2nd sequence timing signal sequencing for the second possible sequence is shown in figure 16. backfeed_cut* goes from low to high and slp_s5* goes from high to low, 30 m sec to 65 m sec (t3) later. latched_backfeed_cut goes high when backfeed_cut* goes high and then latched_backfeed_cut returns to low when slp_s5* goes low. backfeed_cut* stays high and slp_s5* stays low for an indeterminate time and then slp_s5* will go high. a minimum of 1msec (t4) later, backfeed_cut* will go low and the system is ba ck at the end of the power-up sequence. typical measured values of t4 are 250 msec. during all transitions, the propagation delays, rise and fall times, and going into regulation times for latched_backfeed_cut are as described in figure 16. the first sequence starts can st art at the end of the power-up sequence at any time.
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 23 rsmrst* generation rsmrst* is a delayed 3.3 v hysteresis copy of v_5po_stby. rsmrst* is delayed going inactive from the rising edge of v_5po_stby by 32 ms, nominal. this delay starts when v_5po_stby hits the trip point. there is minimal delay on the falling edge. sw00596 v_5p0_stby rsmrst* max min v trip t reset figure 17. resume reset functionality sw00597 t reset t reset_fall v_5p0_stby rsmrst* figure 18. resume reset functionality during brown out
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 24 audio-disable aud_en pcirst aud_rst 0 0 0 0 1 0 1 0 0 1 1 1 mute audio circuit mute_aud aud_shdn 0 1 1 0 hd single color led driver primary_hd secondary_hd scsi hd_led 0 0 0 0 0 x x 0 x 0 x 0 x x 0 0 1 1 1 hiz ide reset signal generation and pcrist drive strength pcirst ide_rstdrv 1 pcirst_out 0 0 0 1 1 1 note: 1. ide_rstdrv is a 5 v copy of pcirst. pcirst_out is a 3.3 v copy of pcirst. pwrgd signal generation fprst pwrgd_ps pwrgd_3v 0 0 0 0 1 0 1 0 0 1 1 1 flush_out / init_out circuit case a20m gpo_flush_cache init flush_out_cpu flush_out_fwh init_out 1 1 falling edge 0 0(for t1) 0(for t1) 0, hi-z, then 0 (delayed by t1-t, then active for 2*t) 2 1 falling edge 1 0(for t1) 0(for t1) hi-z, 0 (delayed by t1-t, then active for 2*t) 3 x 1 0 hi-z hi-z 0 4 x 1 1 hi-z hi-z hi-z 5 0 falling edge 1 hi-z hi-z hi-z 6 0 falling edge 0 hi-z hi-z 0 clk_in and sel_33_66 sel_33_66 clk_in rate 0 66 mhz 1 33 mhz
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 25 sw00603 clk_in sel_33_66 clk 2 figure 19. gp_in/gp_out general purpose gates gp1_ina gp1_inb gp1_out 0 0 1 0 1 1 1 0 1 1 1 0 gp_in/gp_out general purpose gates (continued) gp2_in gp2_out 0 1 1 0 gp_in/gp_out general purpose gates (continued) gp3_in gp3_out 0 0 1 1 power sequencing / backfeed_cut pwrgd_ps slp_s3 backfeed_cut 0 0 hi-z 0 1 hi-z 1 0 hi-z 1 1 0 power supply turn-on circuit slotocc slp_s3 slp_s3a 0 0 hi-z 0 1 0 1 0 hi-z 1 1 hi-z rambus_sck_bjt pwrgd_3v sck_bjt_gate 0 hi-z 1 0
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 26 vga dcc voltage translation 3v_ddcsda 3v_ddcscl 5v_ddcsda 5v_ddcscl 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 hsync / vsync voltage translation hsync_3v hsync_5v vsync_3v vsync_5v 0 0 0 0 1 1 1 1 power led driver ylw_blnk slp_s5 ylw_led grn_blnk slp_s5 grn_led 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 hi-z 1 1 hi-z
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 27 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 28 revision history rev date description _5 20040511 product data (9397 750 13279). supersedes data of 2003 nov 10 (9397 750 12288). modifications: ? page 24, audio-disable table: aud_en column (reading veritcally) changed from `0000' to `0011'. _4 20031110 product data (9397 750 12288); ecn 853-2206 30409 dated 10 october 2003. supersedes data of 28 march 2003 (9397 750 09602). _3 20030328 product data (9397 750 09602); ecn: 8532206 27930 (2003 mar 28)
philips semiconductors product data PCA9504A glue chip 4 2004 may 11 29 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 05-04 document order number: 9397 750 13279 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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